網(wǎng)絡(luò)釋義

用法例句

An approach to the design of microprogram controller for coprocessor;

一種協(xié)處理器微程序控制器的設(shè)計

Brief History and Prospect of Coprocessors;

簡述協(xié)處理器發(fā)展歷程及前景展望

Study on design of motion estimation coprocessor based on MCU architecture;

基于MCU架構(gòu)的運動估計協(xié)處理器的研究與實現(xiàn)

Design of Median-Filter Co-Processor Based on NiosII;

基于NiosII的中值濾波協(xié)處理器設(shè)計

Design of MAC for wireless sensor networks based on co-processor architecture

基于協(xié)處理器的無線傳感器網(wǎng)絡(luò)MAC設(shè)計

In this paper, the high performance of the parallel processing architecture of NP4GS3C and its hardware co-processor are introduced, and the specific applications of NP4GS3C on high speed router are analyzed as well.

本文介紹了NP4GS3C的高性能的并行處理體系結(jié)構(gòu)和硬件協(xié)處理器,并結(jié)合其特性分析了在高速路由器上的應(yīng)用。

In order to demonstrate the feasibility of using an RSA coprocessor to accelerate the ECC algorithm,we presented a new method for implementing modular inversion which is required by the ECC algorithm.

新方法包括對Montgomery模逆算法的改進和對基于Montgomery模乘的RSA協(xié)處理器的修改。

An attack-resisted RSA coprocessor integrating multiplication and inverse is presented in this paper.

提出了一種集成模乘求逆雙重運算的抗攻擊RSA協(xié)處理器設(shè)計。

An application design is given to show a method and technology in which TCAM co-processor is used to accelerate packet processing efficiency.

文章從TCAM的原理及結(jié)構(gòu)特點出發(fā),闡述了其適用于提高NP性能的原因,通過一個設(shè)計實例說明了采用TCAM協(xié)處理器在網(wǎng)絡(luò)處理器中加速包處理過程的方法和技術(shù)。

The key to the 1553B bus system is the protocol processor.

然而目前國內(nèi)使用的1553B協(xié)議處理器的專用芯片均從國外廠商購買，國內(nèi)并無生產(chǎn)這種專用芯片的技術(shù)。

A new address generator of the embeded SIMD coprocessor is introduced in this paper.

文章介紹了一種新的嵌入式SIMD協(xié)處理器地址產(chǎn)生器。

SW/HW Co-design for CSMA/CA Coprocessor in WSN Node SoC

WSN中CSMA/CA協(xié)處理器的軟硬協(xié)同設(shè)計

Complex SoC Design Based on LEON3 and Speed Coprocessor

基于LEON3處理器和Speed協(xié)處理器的復(fù)雜SoC設(shè)計實現(xiàn)

High performance speech vocoder using SIMD coprocessor

使用SIMD協(xié)處理器的高性能聲碼器

Research and Design on Reconfigurable Coprocessor Architecture for Image-processing Application;

面向圖像處理的可重構(gòu)協(xié)處理器結(jié)構(gòu)設(shè)計研究

Research and Design on a 2048 Bits RSA Co-processor IP Core;

2048位RSA協(xié)處理器IP核的研究與設(shè)計

The Research on ECC Hardware Algorithm and the Implemtation of ECC Co-Processor;

ECC硬件算法研究及協(xié)處理器實現(xiàn)

Design of 8087 Math Coprocessor CMOS Circuit;

8087數(shù)值協(xié)處理器CMOS電路的設(shè)計

Research and Design of IPSec Cryptographic Coprocessor;

IPSec安全協(xié)處理器的研究與設(shè)計

The FPGA Design of AES Processor on the IC Card;

IC卡AES協(xié)處理器的FPGA設(shè)計

THE ANALYSIS AND DESIGN OF 8087 MATH COPROCESSOR;

8087數(shù)值協(xié)處理器的分析與設(shè)計

Research on Acceleration Mechanisms of Custom Instruction and Coprocessor

定制指令與協(xié)處理器加速機制的研究

JPEG Decoding Coprocessor Based on FSL Bus

基于FSL總線的JPEG解碼協(xié)處理器

Design and Verification of Vector Floating Point Coprocessor VFP-A

向量浮點協(xié)處理器VFP-A的設(shè)計和驗證

GRCC:A General Reconfigurable Coprocessor

GRCC:一種通用可重構(gòu)協(xié)處理器

AES Coprocessor Implementation Based on Wireless Sensor Network

基于無線傳感網(wǎng)絡(luò)的AES協(xié)處理器設(shè)計

Application of Graphics Coprocessor SM501 in Video System

圖形協(xié)處理器SM501在視頻系統(tǒng)中的應(yīng)用

The Discussion of Cache Coherence Protocol

多處理器系統(tǒng)cache一致性協(xié)議的探討

Realization of IPSec Protocol Based on IXP2350 Network Processor;

基于網(wǎng)絡(luò)處理器IXP2350的IPSec協(xié)議實現(xiàn)設(shè)計