A digital phase-shifting frequency-dividing clock has been designed with CPLD(Complex Programmable Logic Device) technique which modularizes hardware circuit and integrates different modules into one chip.
設(shè)計(jì)了一種數(shù)字移相分頻鐘 ,其中利用了先進(jìn)的復(fù)雜可編程邏輯器件(CPLD -ComplexProgrammableLogicDevice)技術(shù) ,將硬件電路模塊化 ,把各功能模塊集成在一個(gè)芯片中。